cy2302 frequency multiplier and zero delay buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07154 rev. *e revised march 24, 2011 features 90 ps typical jitter out2 200 ps typical jitter out1 65 ps typical output-to-output skew 90 ps typical propagation delay voltage range: 3.3 v5%, or 5 v10% output frequency range: 5 mhz to 133 mhz two outputs configuration options allow various multiplications of the reference frequency?refer to ta b l e 1 to determine the specific option which meets your multiplication needs available in 8-pin soic package table 1. configuration options fbin fs0 fs1 out1 out2 out1 0 0 2 x ref ref out1 1 0 4 x ref 2 x ref out1 0 1 ref ref/2 out1 1 1 8 x ref 4 x ref out2 0 0 4 x ref 2 x ref out2 1 0 8 x ref 4 x ref out2 0 1 2 x ref ref out2 1 1 16 x ref 8 x ref q fs0 fs1 reference fbin phase detector charge pump loop filter vco 2 output buffer out1 out2 output buffer external feedback connection to out1 or out2, not both input in logic block diagram [+] feedback
cy2302 document #: 38-07154 rev. *e page 2 of 9 pinouts figure 1. pin configuration ? 8-pin soic package out2 vdd out1 fs1 8 7 6 5 fbin in gnd fs0 1 2 3 4 table 2. pin definition pin name pin no pin type pin description in 2 i reference input: the output signals are synchronized to this signal. fbin 1 i feedback input: this input must be fed by one of the outputs (out1 or out2) to ensure proper functionality. if the trace between fbin and the output pin being used for feedback is equal in length to the traces bet ween the outputs and the signal destinations, then the signals received at the destinations are synchronized to the ref signal input (in). out1 6 o output 1: the frequency of the signal provided by this pin is determined by the feedback signal connected to fbin, and the fs0:1 inputs (see ta b l e 1 ). out2 8 o output 2: the frequency of the signal provi ded by this pin is one-half of the frequency of out1. see table 1 . vdd 7 p power connections: connect to 3.3v or 5v. this pin should be bypassed with a 0.1- ? f decoupling capacitor. use ferrite beads to help reduce noise for optimal jitter performance. gnd 3 p ground connection: connect all grounds to the common system ground plane. fs0:1 4, 5 i function select inputs: tie to v dd (high, 1) or gnd (low, 0) as desired per table 1 . [+] feedback
cy2302 document #: 38-07154 rev. *e page 3 of 9 overview the cy2302 is a two-output zero delay buffer and frequency multiplier. it provides an external feedback path allowing maximum flexibility when implementing the zero dela y feature. this is explained further in the sections of this datasheet titled, how to implement zero delay on page 3 , and inserting other devices in feedback path on page 3 . the cy2302 is a pin-compatible upgrade of the cypress w42c70 -01. the cy2302 addresses some application dependent problems experienced by users of the older device. figure 2. schematic/suggested layout how to implement zero delay typically, zero delay buffers (zdbs) are used because a designer wants to provide multiple copies of a clock signal in phase with each other. the whol e concept behind zdbs is that the signals at the destination chips are all going high at the same time as the input to the zdb. in order to achieve this, layout must compensate for trace length between the zdb and the target devices. the method of compensation is described as follows. external feedback is the trait that allows for this compensation. the pll on the zdb causes the feedback signal to be in phase with the reference signal. when laying out the board, match the trace lengths between the output being used for feedback and the fbin input to the pll. if it is desirable to either add a little delay, or sli ghtly precede the input signal, this may also be implemented by either making the trace to the fbin pin a little shor ter or a little longer than the traces to the devices being clocked. inserting other devices in feedback path another nice feature available due to the external feedback is the ability to synchronize signals to the signal coming from some other device. this implementation can be applied to any device (asic, multiple output clock buffer/dr iver, etc.) that is put into the feedback path. referring to figure 2 , if the traces between the asic/buffer and the destination of the clock signal(s) (a) are equal in length to the trace between the buffer and the fbin pin, the signals at the destination(s) device is driven high at the same time when the reference clock provided to the zdb goes high. synchronizing the other outputs of the zdb to the outputs from the asic/buffer is more complex however, as any propagation delay from the zdb output to the asic/buffer output must be accounted for. figure 3. six output buffer in the feedback path phase alignment in cases where out1 (i.e., the higher frequency output) is connected to fbin input pin the output out2 rising edges may be either 0 or 180 phase aligned to the in input waveform (as set randomly when the input and/or power is supplied). if out2 is desired to be rising-edge aligned to the in input?s rising edge, then connect the out2 (i.e., t he lowest frequency output) to the fbin pin. this set-up provides a consistent inpu t-output phase relationship. c8 g ferrite bead power supply connection v+ g c a g fs1 fs0 gnd in fbin 10 f 0.01 f 1 2 3 4 8 7 6 5 ? ? 22 ? 22 ? g c9 = 0.1 f output 1 output 2 out 2 v dd out 1 reference signal feedback input asic/ buffer zero delay buffer a [+] feedback
cy2302 document #: 38-07154 rev. *e page 4 of 9 absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. . parameter description rating unit v dd , v in voltage on any pin with respect to gnd ?0.5 to +7.0 v t stg storage temperature ?65 to +150 c t a ambient operating temperature, commercial 0 to +70 c ambient operating te mperature, industrial ?40 to +85 c t b ambient temperature under bias ?55 to +125 c p d power dissipation 0.5 w dc electrical characteristics t a = 0 c to 70 c or ?40 c to 85 c, v dd = 3.3 v 5% parameter description test condition min typ max unit i dd supply current unloaded, 100 mhz ? 17 35 ma v il input low voltage ? ? ? 0.8 v v ih input high voltage ? 2.0 ? ? v v ol output low voltage i ol = 12 ma ? ? 0.4 v v oh output high voltage i oh = -12 ma 2.4 ? ? v i il input low current v in = 0v ?40 ? 5 ? a i ih input high current v in = v dd ?? 5 ? a dc electrical characteristics t a = 0 c to 70 c or ?40 c to 85 c, v dd = 5 v 10% parameter description test condition min typ max unit i dd supply current unloaded, 100 mhz ? 37 50 ma v il input low voltage ? ? ? 0.8 v v ih input high voltage ? 2.0 ? ? v v ol output low voltage i ol = 12 ma ? ? 0.4 v v oh output high voltage i oh = -12 ma 2.4 ? ? v i il input low current v in = 0 v ?80 ? 5 ? a i ih input high current v in = v dd ?? 5 ? a [+] feedback
cy2302 document #: 38-07154 rev. *e page 5 of 9 notes 1. input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration). 2. longer input rise and fall time degrades skew and jitter performance. 3. all ac specifications are measured with a 50 ? transmission line, load terminated with 50 ? to 1.4 v. 4. skew is measured at 1.4 v on rising edges. 5. duty cycle is measured at 1.4 v. 6. 33 mhz reference input suddenly stopped (0 mhz). number of cycles provided prior to output falling to <16 mhz. 7. duty cycle measured at 120 mhz. for 133 mhz, degrades to 35/65 worst case. ac electrical characteristics t a = 0c to +70c or ?40 to 85c, v dd = 3.3v 5% [3] parameter description test condition min typ max unit f in input frequency [1] ?5?133mhz f out output frequency out1 15-pf load 10 ? 133 mhz t r output rise time 0.8 v to 2.0 v, 15-pf load ? ? 3.5 ns t f output fall time 2.0 v to 0.8 v, 15-pf load ? ? 2.5 ns t iclkr input clock rise time [2] ???10ns t iclkf input clock fall time [2] ???10ns t d duty cycle 15-pf load [5] 40 50 60 % t lock pll lock time power supply stable ? ? 1.0 ms t jc jitter, cycle-to -cycle out1, f out >30 mhz ? 200 300 ps out2, f out >30 mhz ? 90 300 ps t dc die out time [6] ? 100 ? ? clock cycles t skew output-output skew [4] ??65250ps t pd propagation delay [4] ? ?350 90 350 ps ac electrical characteristics t a = 0c to +70c or ?40 to 85c, v dd = 5.0v 10% [3] parameter description test condition min typ max unit f in input frequency [1] ?5?133mhz f out output frequency out1 15-pf load 10 ? 133 mhz t r output rise time 0.8 v to 2.0 v, 15-pf load ? ? 2.5 ns t f output fall time 2.0 v to 0.8 v, 15-pf load ? ? 1.5 ns t iclkr input clock rise time [2] ???10ns t iclkf input clock fall time [2] ???10ns t d duty cycle 15-pf load [5, 7] 40 50 60 % t lock pll lock time power supply stable ? ? 1.0 ms t jc jitter, cycle-to-cycle out1, f out >30 mhz ? 200 300 ps out2, f out >30 mhz ? 90 300 ps t dc die out time [6] ? 100 ? ? clock cycles t skew output-output skew [4] ? ? 65 250 ps t pd propagation delay [4] ? ?350 90 350 ps [+] feedback
cy2302 document #: 38-07154 rev. *e page 6 of 9 ordering information ordering code package type temperature grade pb-free cy2302sxc-1 8-pin soic commercial (0 to 70 c) cy2302sxc-1t 8-pin soic ? tape and reel commercial (0 to 70 c) cy2302sxi-1 8-pin soic industrial (?40 to 85 c) CY2302SXI-1T 8-pin soic ? tape and reel industrial (?40 to 85 c) ordering code definitions t = tape and reel, blank = standard dash or variant code temperature range c = commercial = 0 c to +70 c i = industrial = ?40 c to +85 c pb free, blank = leaded package type s = soic part identifier company id: cy = cypress xxxx cy x x i (-x) t [+] feedback
cy2302 document #: 38-07154 rev. *e page 7 of 9 package diagram figure 4. 8-pin (150-mil) soic s8 51-85066 *d [+] feedback
cy2302 document #: 38-07154 rev. *e page 8 of 9 acronyms document conventions units of measure acronym description fbk feedback pll phase locked loop mux multiplexer symbol unit of measure symbol unit of measure c degrees celsius w microwatts db decibels ma milliamperes fc femtocoulomb mm millimeters ff femtofarads ms milliseconds hz hertz mv millivolts kb 1024 bytes na nanoamperes kbit 1024 bits ns nanoseconds khz kilohertz nv nanovolts k ? kilohms ? ohms mhz megahertz pa picoamperes m ? megaohms pf picofarads a microamperes pp peak-to-peak f microfarads ppm parts per million h microhenrys ps picoseconds s microseconds sps samples per second v microvolts ? sigma: one standard deviation vrms microvolts root-mean-square [+] feedback
document #: 38-07154 rev. *e revised march 24, 2011 page 9 of 9 all products and company names mentioned in this document may be the trademarks of their respective holders. cy2302 ? cypress semiconductor corporation, 2001-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document title: cy2302 frequency multiplier and zero delay buffer document number: 38-07154 revision ecn orig. of change submission date description of change ** 110264 szv 12/18/01 change from spec number: 38-00794 to 38-07154 *a 394695 rgl see ecn added typical char data added pb-free devices added phase alignment paragraph *b 2761988 kvm 09/10/09 removed cy2302si-1t from the ordering information table added temperature values to ordering information table and to absolute maximum table *c 2894970 kvm 03/23/2010 removed inactive parts from ordering information table. updated package diagram . *d 2907904 kvm 04/08/2010 removed inactive parts from ordering information table. *e 3204657 bash 03/24/2011 added ordering code definitions, acronyms, and document conventions. [+] feedback
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